Low power high speed digital arithmetic circuit /
Khallid Hussien Mahmoud Khallaf
Low power high speed digital arithmetic circuit / الدوائر الحسابية الرقمية منخفضة القدرة عالية السرعة Khallid Hussien Mahmoud Khallaf ; Supervised Abdelhalim Shousha , Ahmed Tarek Sayed - Cairo : Khallid Hussien Mahmoud Khallaf , 2010 - 78 P. : charts , facsimiles ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
We explored the main building block of most arithmetic digital circuits viz . The full adder . We surveyed the most recent published full adder cells . We designed them simulated and measured their power consumption and delays . We identified key sub-circuits that are critical to power consumption
Full adder Low power Power consumption
Low power high speed digital arithmetic circuit / الدوائر الحسابية الرقمية منخفضة القدرة عالية السرعة Khallid Hussien Mahmoud Khallaf ; Supervised Abdelhalim Shousha , Ahmed Tarek Sayed - Cairo : Khallid Hussien Mahmoud Khallaf , 2010 - 78 P. : charts , facsimiles ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
We explored the main building block of most arithmetic digital circuits viz . The full adder . We surveyed the most recent published full adder cells . We designed them simulated and measured their power consumption and delays . We identified key sub-circuits that are critical to power consumption
Full adder Low power Power consumption