Enhanced performance of Cairo University SPARC processor at 65nm node /
Alhassan Mohamed Fattin Mohamed Zaki Khedr
Enhanced performance of Cairo University SPARC processor at 65nm node / تحسين أداء معالج SPARC المطور بجامعة القاهرة بتكنولوجيا 65 نانومتر Alhassan Mohamed Fattin Mohamed Zaki Khedr ; Supervised Serag E. D. Habib - Cairo : Alhassan Mohamed Fattin Mohamed Zaki Khedr , 2011 - 84P. : charts , plans ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
Several enhancements to the CUSPARC design are reported in this rhesis . First , to enhance its DSP performance , the CUSPARC design is augmented with an energy efficient 32 - bit integer multiplier. Second, the source code of the GCC compiler is customized to support the added multiplier. Third, the processor design is ported to the TSMC 65nm CMOS technology node
65nm CUSPARC processor GCC Compiler
Enhanced performance of Cairo University SPARC processor at 65nm node / تحسين أداء معالج SPARC المطور بجامعة القاهرة بتكنولوجيا 65 نانومتر Alhassan Mohamed Fattin Mohamed Zaki Khedr ; Supervised Serag E. D. Habib - Cairo : Alhassan Mohamed Fattin Mohamed Zaki Khedr , 2011 - 84P. : charts , plans ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
Several enhancements to the CUSPARC design are reported in this rhesis . First , to enhance its DSP performance , the CUSPARC design is augmented with an energy efficient 32 - bit integer multiplier. Second, the source code of the GCC compiler is customized to support the added multiplier. Third, the processor design is ported to the TSMC 65nm CMOS technology node
65nm CUSPARC processor GCC Compiler