A single core fpga aes cipher\decipher for key lengths of 128, 192 and 256 bits /
Ahmed Mohamed Abdelmawgoud Ragab
A single core fpga aes cipher\decipher for key lengths of 128, 192 and 256 bits / لأطوال المفاتيح192:128و 256 بت AES تحقيق نظام تشفير/ فك تشفيرٍعلى دائرة منطقية قابلة للبرمجة بنواة واحدة للنظام Ahmed Mohamed Abdelmawgoud Ragab ; Supervised Ahmed H. Khalil , Hisham M. Hamed - Cairo : Ahmed Mohamed Abdelmawgoud Ragab , 2016 - 109 P. ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
This work present an optimized pipelined hardware implementation of the advanced encryption standard (AES) with key lengths of 128, 192 and 256 bits on an altera stratix III-EP3SL150F1152 field programmable gate array (FPGA). Starting from an architecture dedicated to 256-bit key operations, a series of optimization are performed to allow the handling of 128-bit and 192-bit keys, using one core, rather than three separate cores. The various operations required for the AES algorithm are thus analyzed from a hardware implementation perspective. The system throughput is also enhanced through the simultaneous calculations of operations. In the timing report, the system frequency reaches a maximum of 332 MHz producing a maximum throughput of 42.48 Gbps with a latency ranges from 21 to 29 clk cycles depending on the selected operation. The design was tested on a terasic DE3-150 development board at 100 MHZ, and operated with the Altera-NiosII CPU environment
AES FPGA Operations sharing
A single core fpga aes cipher\decipher for key lengths of 128, 192 and 256 bits / لأطوال المفاتيح192:128و 256 بت AES تحقيق نظام تشفير/ فك تشفيرٍعلى دائرة منطقية قابلة للبرمجة بنواة واحدة للنظام Ahmed Mohamed Abdelmawgoud Ragab ; Supervised Ahmed H. Khalil , Hisham M. Hamed - Cairo : Ahmed Mohamed Abdelmawgoud Ragab , 2016 - 109 P. ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
This work present an optimized pipelined hardware implementation of the advanced encryption standard (AES) with key lengths of 128, 192 and 256 bits on an altera stratix III-EP3SL150F1152 field programmable gate array (FPGA). Starting from an architecture dedicated to 256-bit key operations, a series of optimization are performed to allow the handling of 128-bit and 192-bit keys, using one core, rather than three separate cores. The various operations required for the AES algorithm are thus analyzed from a hardware implementation perspective. The system throughput is also enhanced through the simultaneous calculations of operations. In the timing report, the system frequency reaches a maximum of 332 MHz producing a maximum throughput of 42.48 Gbps with a latency ranges from 21 to 29 clk cycles depending on the selected operation. The design was tested on a terasic DE3-150 development board at 100 MHZ, and operated with the Altera-NiosII CPU environment
AES FPGA Operations sharing