Continuous-time sigma-delta modulator using a novel ring amplifier architecture /
Amr Ahmed Saad Ahmed
Continuous-time sigma-delta modulator using a novel ring amplifier architecture / معدل سيجما دلتا مستمر الوقت باستخدام اسلوب بناء جديد للمكبر الحلقي Amr Ahmed Saad Ahmed ; Supervised Ahmed Nader Mohieldin , Mohamed M. Aboudina , Faisal A. Hussien - Cairo : Amr Ahmed Saad Ahmed , 2018 - 97 P. : charts , facsimiles ; 25cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
In this thesis a novel ring amplifier architecture is proposed. This structure is the first of its kind in which it enables the usage of ring amplifier in continuous time applications. The new structure design and design equations is clarified with the help of a design example of second order continuous time modulator. Then, the proposed architecture is used to implement a more complex third order, 1.5 bit quantizer V4 modulator. The modulator is implemented in a 65nm CMOS technology and can achieves a SNDR of 66 dB for a 5 MHz BW input signal while consuming only 1.5 mW from a 0.9 V single supply. Hence, achieving a Figure of Merit (FoM) of 92 fJ/Conv
Analog to Digital Converter Ring Amplifier Sigma-Delta ADC
Continuous-time sigma-delta modulator using a novel ring amplifier architecture / معدل سيجما دلتا مستمر الوقت باستخدام اسلوب بناء جديد للمكبر الحلقي Amr Ahmed Saad Ahmed ; Supervised Ahmed Nader Mohieldin , Mohamed M. Aboudina , Faisal A. Hussien - Cairo : Amr Ahmed Saad Ahmed , 2018 - 97 P. : charts , facsimiles ; 25cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
In this thesis a novel ring amplifier architecture is proposed. This structure is the first of its kind in which it enables the usage of ring amplifier in continuous time applications. The new structure design and design equations is clarified with the help of a design example of second order continuous time modulator. Then, the proposed architecture is used to implement a more complex third order, 1.5 bit quantizer V4 modulator. The modulator is implemented in a 65nm CMOS technology and can achieves a SNDR of 66 dB for a 5 MHz BW input signal while consuming only 1.5 mW from a 0.9 V single supply. Hence, achieving a Figure of Merit (FoM) of 92 fJ/Conv
Analog to Digital Converter Ring Amplifier Sigma-Delta ADC