Exploring the simulation of dynamic partial reconfiguration for network on chip (NOC)-based FPGA /
Amr Hassan Ali Baddar
Exploring the simulation of dynamic partial reconfiguration for network on chip (NOC)-based FPGA / استكشاف محاكاة إعادة التشكيل الجزئي الديناميكي لتطبيق شبكات توصيل المعلومات على نظم المصفوفات القابله للبرمجه Amr Hassan Ali Baddar ; Supervised Hossam A. H. Fahmy , Hassan Mostafa - Cairo : Amr Hassan Ali Baddar , 2019 - 68 P. : charts , facsimiles ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
In this thesis, a literature survey of exiting Dynamic Partial Reconfiguration (DPR) techniques forconventional FPGAsis presented. Then, a comparative review ofthese techniques is providedwith respect to reconfiguration time and area. Following that, different network parameters at the NoC-based FPGAs have been analyzed to estimate the impact on DPR performance usinga state-of-art simulator2NoC-DPR3, Finally, a case study is introduced to clarify the DPR performancegap between NoC-based FPGAs and conventional FPGAs
Dynamic Partial Reconfiguration Fields Programmable Gate Array Network-on-Chip
Exploring the simulation of dynamic partial reconfiguration for network on chip (NOC)-based FPGA / استكشاف محاكاة إعادة التشكيل الجزئي الديناميكي لتطبيق شبكات توصيل المعلومات على نظم المصفوفات القابله للبرمجه Amr Hassan Ali Baddar ; Supervised Hossam A. H. Fahmy , Hassan Mostafa - Cairo : Amr Hassan Ali Baddar , 2019 - 68 P. : charts , facsimiles ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
In this thesis, a literature survey of exiting Dynamic Partial Reconfiguration (DPR) techniques forconventional FPGAsis presented. Then, a comparative review ofthese techniques is providedwith respect to reconfiguration time and area. Following that, different network parameters at the NoC-based FPGAs have been analyzed to estimate the impact on DPR performance usinga state-of-art simulator2NoC-DPR3, Finally, a case study is introduced to clarify the DPR performancegap between NoC-based FPGAs and conventional FPGAs
Dynamic Partial Reconfiguration Fields Programmable Gate Array Network-on-Chip