A low-power sub-sampling all-digital phase-locked loop with fast frequency-correction capability /
Omar Hamada Eid Seif Hassan
A low-power sub-sampling all-digital phase-locked loop with fast frequency-correction capability / حلقة إغلاق على الطور رقمية كليا منخفضة الطاقة بتقنية اختزال العينات مع القدرة على التصحيح السريع للتردد Omar Hamada Eid Seif Hassan ; Supervised Ahmed Nader Mohieldin , Mohamed Mostafa Aboudina - Cairo : Omar Hamada Eid Seif Hassan , 2020 - 141 P . : charts ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
In this thesis, a low-power all-digital phase-locked loop (ADPLL) is presented to be used as a frequency synthesizer in low-power applications. The PLL utilizes sub-sampling operation to maintain low power consumption. A novel technique is proposed to extend the loops lock-in range. This technique allows the loop to tolerate 10x larger frequency disturbances without losing locking. The main analog blocks are designed in a 40nm CMOS technology. A new time to digital converter (TDC) architecture based on a multi-path delay line is introduced. The new architecture allows the TDC to achieve high resolution while keeping a low power consumption. An 8-bit segmented digital to time converter (DTC) is designed. The DTC achieves relatively good linearity while consuming low power. A low-power digitally-controlled oscillator (DCO) is implemented and it achieves better than -114dBc/Hz phase noise at 1MHz offset. The estimated PLL phase noise at 1MHz offset is around -109dBc/Hz
All-digital PLL Lock-in range extension Time to Digital Converter
A low-power sub-sampling all-digital phase-locked loop with fast frequency-correction capability / حلقة إغلاق على الطور رقمية كليا منخفضة الطاقة بتقنية اختزال العينات مع القدرة على التصحيح السريع للتردد Omar Hamada Eid Seif Hassan ; Supervised Ahmed Nader Mohieldin , Mohamed Mostafa Aboudina - Cairo : Omar Hamada Eid Seif Hassan , 2020 - 141 P . : charts ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
In this thesis, a low-power all-digital phase-locked loop (ADPLL) is presented to be used as a frequency synthesizer in low-power applications. The PLL utilizes sub-sampling operation to maintain low power consumption. A novel technique is proposed to extend the loops lock-in range. This technique allows the loop to tolerate 10x larger frequency disturbances without losing locking. The main analog blocks are designed in a 40nm CMOS technology. A new time to digital converter (TDC) architecture based on a multi-path delay line is introduced. The new architecture allows the TDC to achieve high resolution while keeping a low power consumption. An 8-bit segmented digital to time converter (DTC) is designed. The DTC achieves relatively good linearity while consuming low power. A low-power digitally-controlled oscillator (DCO) is implemented and it achieves better than -114dBc/Hz phase noise at 1MHz offset. The estimated PLL phase noise at 1MHz offset is around -109dBc/Hz
All-digital PLL Lock-in range extension Time to Digital Converter