MARC details
| 000 -LEADER |
|---|
| fixed length control field |
04412namaa22004451i 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20240211192447.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
2310s2022 xao frm 000 engnd d |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
EG-GICUC |
| Language of cataloging |
eng |
| Transcribing agency |
EG-GICUC |
| Modifying agency |
EG-GICUC |
| Description conventions |
rda |
| 041 0# - LANGUAGE CODE |
|---|
| Language code of text/sound track or separate title |
eng |
| Language code of summary or abstract |
eng |
| -- |
ara |
| 049 ## - LOCAL HOLDINGS (OCLC) |
|---|
| Holding library |
Deposit |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.6 |
| Edition number |
21 |
| 092 ## - LOCALLY ASSIGNED DEWEY CALL NUMBER (OCLC) |
|---|
| Classification number |
004.6 |
| Edition number |
21 |
| 097 ## - Thesis Degree |
|---|
| Thesis Level |
M.Sc |
| 099 ## - LOCAL FREE-TEXT CALL NUMBER (OCLC) |
|---|
| Classification number |
Cai01.13.08.M.Sc.2022.Mo.H |
| 100 0# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Mohamed Nafea Mohamed Nafea Khalifa, |
| Relator term |
preparation. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Hardware/software co-design implementation for cnn model using memory tiling / |
| Statement of responsibility, etc. |
Mohamed Nafea Mohamed Nafea Khalifa ; Amin M. Nassar, Omar A. Nasr, Hassan Mostafa. |
| 246 ## - VARYING FORM OF TITLE |
|---|
| Title proper/short title |
تنفيذ تصميم نموذج الشبكة العصبية التلافيفية بتقسيم التصميم بين العتاد والبرمجيات باستخدام تبليط الذاكرة |
| 264 #0 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Date of production, publication, distribution, manufacture, or copyright notice |
2022. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
100 Pages : |
| Other physical details |
Illustrations, Photograph ; |
| Dimensions |
25 cm. + |
| Accompanying material |
CD. |
| 336 ## - CONTENT TYPE |
|---|
| Source |
rda content |
| Content type term |
text |
| 337 ## - MEDIA TYPE |
|---|
| Source |
rdamedia |
| Media type term |
Unmediated |
| 338 ## - CARRIER TYPE |
|---|
| Source |
rdacarrier |
| Carrier type term |
volume |
| 502 ## - DISSERTATION NOTE |
|---|
| Dissertation note |
Thesis (M.Sc.)-Cairo University, Faculty of Engineering, Department of Electronics and Communications,2022. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Bibliography: Pages 91-95. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
الشبكات العصبية التلافيفية (CNN) تم استخدمها مؤخرًا في العديد من التطبيقات. العدد الهائل من العمليات المكثفة في نماذج CNN من الصعب تحقيق مستويات الأداء المطلوبة باستخدام معالجات CPU. لذلك، تم تطوير مسرعات أجهزة مختلفة لشبكات CNN العميقة مؤخرًا لتحسين الإنتاجية، مسرعات FPGA هي الأكثر شيوعا. في هذا العمل، يتم اتباع منهجية تقسيم التصميم المشترك (HW/SW) باستخدام أداة Xilinx SDSoC لاقتراح مسرّع عالي المستوى يعتمد على FPGA في نموذج GoogLeNet CNN.قمنا بتطوير تطبيقات(C++)عالية المستوى تستخدم الموارد المتاحة لتحقيق أقصى أداء. المسرع المقترح يدعم دقة بيانات مختلفة مثلالنقطة العائمة، والنقطة العائمة النصفية، ودقة البيانات الثابتة. تُظهر النتائج التجريبية تسريعًا قدره 48x لدقة بيانات 32-bit floating، مع 3.8 واط لإجمالي استهلاك الطاقة على الرقاقة. يستهلك المسرع المقترح موارد FPGA أقل بنسبة 40٪ من مسرع RTL المقابل |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Convolution Neural Networks (CNNs) are recently deployed in many applications. The massive number of network parameters and the intensive operations in CNN models make it challenging to achieve desired performance levels using general-purpose processors. Therefore, different hardware accelerators for deep CNNs have recently been developed to improve throughput. FPGA-based accelerators are mostly used. In this work, a Hardware/Software (HW/SW) Co-design Partitioning methodology is followed using the Xilinx SDSoC tool to propose a High-Level Synthesis (HLS) FPGA-based accelerator for the GoogLeNet CNN model. Different loop optimization techniques are deployed to allow convolutional functions to run on hardware. The proposed accelerator supports different data precisions. Experimental results show a speedup of 48x for 32-bit float data precision, with 3.8 watts for total on-chip power consumption. The proposed accelerator consumes 40% less FPGA resources than the corresponding RTL accelerator |
| 530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE |
|---|
| Additional physical form available note |
Issues also as CD. |
| 546 ## - LANGUAGE NOTE |
|---|
| Language note |
Text in English and abstract in Arabic & English. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer networks |
| General subdivision |
Management |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic data processing |
| General subdivision |
Certification. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
R (Computer program language). |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Hardware Acclerators |
| -- |
GoogLeNet |
| -- |
Convolutional Neural Networks (CNNs) |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Omar A. Nasr, |
| Relator term |
thesis advisor. |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Hassan Mostafa, |
| Relator term |
thesis advisor. |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Amin M. Nassar, |
| Relator term |
thesis advisor. |
| 900 ## - EQUIVALENCE OR CROSS-REFERENCE-PERSONAL NAME [LOCAL, CANADA] |
|---|
| Numeration |
01-01-2022. |
| Titles and other words associated with a name |
Amin M. Nassar |
| -- |
Omar A. Nasr |
| -- |
Hassan Mostafa |
| Dates associated with a name |
Mohsen Abd El Razik Rashwan |
| -- |
Ahmed Hassan Kamel Madian |
| Universities |
Cairo University |
| Faculties |
Faculty of Engineering |
| Divisons |
Department of Electronics and Communications |
| 905 ## - LOCAL DATA ELEMENT E, LDE (RLIN) |
|---|
| Cataloger |
Mohamady |
| Reviser |
Hanan |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Thesis |
| Source of classification or shelving scheme |
Dewey Decimal Classification |
