ASIC implementation of an all digital delay locked loop ADDLL / Mohamed Gamal Eldin Ahmed Egila ; Supervised Serag Eldin Habib , Nivin Abuelhadid
Language: Eng Publication details: Cairo : Mohamed Gamal Eldin Ahmed Egila , 2008Description: 68P. : plans ; 30cmOther title:- تصميم دائرة متكاملة لحلقة رقمية بالكامل لضبط التأخير [Added title page title]
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قاعة الرسائل الجامعية - الدور الاول | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2008.Mo.A (Browse shelf(Opens below)) | Not for loan | 01010110049917000 | ||
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مخـــزن الرســائل الجـــامعية - البدروم | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2008.Mo.A (Browse shelf(Opens below)) | 49917.CD | Not for loan | 01020110049917000 |
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Thesis (M.Sc.) - Cairo University - Faculty Of Engineering - Department Of Electronics and Communications
Clock recovery circuits are basic components in today's VLSI circuits.Delay locked loops (DLLs) are attractive solutions for clock recovery due to their stability , low latency and the absence of phase error accumulation.All digital DLLs (ADDLL) have the added advantage of simple design and compatibility with mainstream digital design flows
Issued also as CD
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