A new low - power high - performance logic family / Orouba Faraj Alali ; Supervised Aly Ezzat Salama

By:

Orouba Faraj Alali

Contributor(s):

Aly Ezzat Salama []

Language: Eng Publication details: Cairo : Orouba Faraj Alali , 2005Description: 110P : charts ; 30cmOther title:

عائلة منطقية جديدة : منخفضة - الطاقة خالية - السرعة [Added title page title]

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Issued also as CD

Dissertation note: Thesis (PH.D.) - Cairo University - Faculty Of Engineering - Department Of Electronics and Communications Summary: In this thesis , we presented a new logic family , referred as clock - pulse control MOS current mode logic (CPC - MCML) The new logic utilizes the clock - pulse control scheme to reduce dynamic power and enhance performance by putting

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Holdings
Item type	Current library	Home library	Call number	Status	Barcode
Thesis	قاعة الرسائل الجامعية - الدور الاول	المكتبة المركزبة الجديدة - جامعة القاهرة	Cai01.13.08.Ph.D.2005.Or.N. (Browse shelf(Opens below))	Not for loan	01010110043995000
CD - Rom	مخـــزن الرســائل الجـــامعية - البدروم	المكتبة المركزبة الجديدة - جامعة القاهرة	Cai01.13.08.Ph.D.2005.Or.N. (Browse shelf(Opens below))	Not for loan	01020110043995000

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Thesis (PH.D.) - Cairo University - Faculty Of Engineering - Department Of Electronics and Communications

In this thesis , we presented a new logic family , referred as clock - pulse control MOS current mode logic (CPC - MCML) The new logic utilizes the clock - pulse control scheme to reduce dynamic power and enhance performance by putting

Issued also as CD

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