Binary floating point fused multiply add unit / Walaa Abdelaziz Ibrahim ; Supervised Ahmed Hussein Khalil , Hossam Aly Fahmy
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TextLanguage: English Publication details: Cairo : Walaa Abdelaziz Ibrahim , 2012Description: 88P. : charts ; 30cmOther title: - وحدة جمع وضرب مدمجتين للارقام العائمة الثنائية [Added title page title]
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قاعة الرسائل الجامعية - الدور الاول | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2012.Wa.B (Browse shelf(Opens below)) | Not for loan | 01010110058191000 | ||
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مخـــزن الرســائل الجـــامعية - البدروم | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2012.Wa.B (Browse shelf(Opens below)) | 58191.CD | Not for loan | 01020110058191000 |
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| Cai01.13.08.M.Sc.2012.Sa.T Tuning of PD controllers using enhanced genetic algorithms with application to flexible robot systems / | Cai01.13.08.M.Sc.2012.Sh.E Error correction in floating point units using information redundancy / | Cai01.13.08.M.Sc.2012.Sh.E Error correction in floating point units using information redundancy / | Cai01.13.08.M.Sc.2012.Wa.B Binary floating point fused multiply add unit / | Cai01.13.08.M.Sc.2012.Wa.B Binary floating point fused multiply add unit / | Cai01.13.08.M.Sc.2012.Wa.H High performance memory requests scheduling technique for multicore processors / | Cai01.13.08.M.Sc.2012.Wa.H High performance memory requests scheduling technique for multicore processors / |
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
Fused multiply add operation is very important in many scientific application . Many floating - point fused multiply add algorithms are developed to reduce the overall latency of the operation . The greatest deviation from the original IBM RS / 6000 architecture comes from a paper by T. Lang and J. D. Brugurea in 2005 . The main objective of our work is to implement this algorithm but with little change to facilitate the implementation without affecting the performance
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