Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication

Ultra low duty - cycle clock signal is required in buck converters with large step - down voltage conversion ratio. Given the maximum achievable rise and fall time as well as the minimum ON time of the transistors, this sets a maximum limit on the operating frequency. Di erent buck converter architectures are proposed to achieve the same voltage conversion ratio with a larger duty cycle. Therefore, the constraints on the minimum transistor ON time and the maximum operating frequency are relaxed. The proposed converters are completely independent on mutual coupling and, as a consequence, they do not su er from any leakage inductance and do not need any protection or clamping circuits. The three proposed architectures are completely independent on each other, which means that every two architectures can be combined together producing extra architecture for further duty-cycle improvement. Also the three architectures can be combined producing extreme improvement of the duty - cycle. The analysis produces the relation between the duty - cycle and the voltage gain and shows how much the improvements are. The performance of each architecture is nally evaluated and compared to the basic conventional buck converter

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