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Back-end enhancements for Cairo University hardware/software partitioning tool (CUPSHOP) / Rania Osama Hassan Hassan ; Supervised Serag Eldin Elsayed Habib , Mohamed Bakr Abdelhalim Osman

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Rania Osama Hassan Hassan , 2015Description: 106 P. : charts ; 30cmOther title:
  • تعزيزالواجهة الخلفية لأداة جامعة القاهرة الخاصة بتقسيم التصميم بين العتاد والبرمجيات [Added title page title]
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  • Issued also as CD
Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication Summary: In this thesis, several additions and enhancements of Cairo University Particle Swarm Hardware sOftware Partitioning tool (CUPSHOP) are introduced. First, a new delay estimation formula is proposed for guiding the HW/SW partitioning algorithm. This formula enables accurate pre-scheduling delay estimation for each partitioning vector. Second, the pipelined alternative for hardware implementations is added due to its practical importance, high speed and low cost. Third, we developed an automatic VHDL code generation capability for the hardware mapped components
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Item type Current library Home library Call number Copy number Status Date due Barcode
Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2015.Ra.B (Browse shelf(Opens below)) Not for loan 01010110066288000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2015.Ra.B (Browse shelf(Opens below)) 66288.CD Not for loan 01020110066288000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication

In this thesis, several additions and enhancements of Cairo University Particle Swarm Hardware sOftware Partitioning tool (CUPSHOP) are introduced. First, a new delay estimation formula is proposed for guiding the HW/SW partitioning algorithm. This formula enables accurate pre-scheduling delay estimation for each partitioning vector. Second, the pipelined alternative for hardware implementations is added due to its practical importance, high speed and low cost. Third, we developed an automatic VHDL code generation capability for the hardware mapped components

Issued also as CD

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