Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Computer Engineering

We propose a new digit serial - serial multiplier that reduces area compared with standard parallel multiplier and other state - o f- the- art digit serial - serial multiplier. We present the capabilities of the proposed design such as two's complement support, dynamic operand width support and bit-level pipelining support. Then, we use the proposed multiplier as a building block to build a reconfigurable power efficient digit serial - serial multiplier. The reconfigurable design enables single sub-width and multiple - concurrent sub - width multiplications. We use clock gating to further optimize power consumption of the circuit. The design is compared with non - power - optimized version, and the standard parallel multiplier with respect to power, area and latency, and energy. A variant of the multiplier using a different building block is implemented and compared to the original multiplier. We simulated the designs using VHDL then implemented those using ASIC libraries to calculate the design aspects values. We present the results with thorough analysis of the results trends

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