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Proposed opengl GPU architecture and implementation of line rasterization algorithm / Ahmed Ibrahim Samir Khalil ; Supervised Serag E. D. Habib , Hossam A. H. Fahmy

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Ahmed Ibrahim Samir Khalil , 2015Description: 125 P. ; 30cmOther title:
  • بن{u٠٦أأ}ة مقترحة لوحدة معالجة الرسوم{u٠٦أأ}ات وفقا لمكتبة الرسوم{u٠٦أأ}ات المفتوحة و تنف{u٠٦أأ}ذ خوارزم{u٠٦أأ}ة تنق{u٠٦أأ}ط الخط [Added title page title]
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Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Summary: The GPU has become an essential block for the embedded system devices. This thesis introduces a CUGPU, the Cairo University GPU, architecture based on the openGL ES 1.1 CL pro{uFB01}le. CUGPU supports the {uFB01}xed - function 3D graphics pipeline. Also, two designs of the line rasterization algorithm were implemented using VHDL code and synthesized at the TSMC 65 nm low power technology node. The {uFB01}rst design scores a typical clock frequency of 270 MHz and an area of 0.088 mm² . The second design scores a typical clock frequency of 200 MHz and an area of 0.052 mm²
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Item type Current library Home library Call number Copy number Status Date due Barcode
Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2015.Ah.P (Browse shelf(Opens below)) Not for loan 01010110067622000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2015.Ah.P (Browse shelf(Opens below)) 67622.CD Not for loan 01020110067622000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

The GPU has become an essential block for the embedded system devices. This thesis introduces a CUGPU, the Cairo University GPU, architecture based on the openGL ES 1.1 CL pro{uFB01}le. CUGPU supports the {uFB01}xed - function 3D graphics pipeline. Also, two designs of the line rasterization algorithm were implemented using VHDL code and synthesized at the TSMC 65 nm low power technology node. The {uFB01}rst design scores a typical clock frequency of 270 MHz and an area of 0.088 mm² . The second design scores a typical clock frequency of 200 MHz and an area of 0.052 mm²

Issued also as CD

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