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Asynchronous sar-assisted two-stage pipeline analog to digital converter using ring amplifier / Karim Moataz Mohamed Mahmoud Ali Megawer ; Supervised Ahmed Nader Mohieldin , Mohamed M. Aboudina , Faisal A. Hussien

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Karim Moataz Mohamed Mahmoud Ali Megawer , 2016Description: 103 P. : charts , facsimiles ; 30cmOther title:
  • محول بيانات تناظرى رقمى غير متزامن بتقنية انبوبة المرحلتين بمساعدة التقريب المتوالى واستخدام مكبر حلقى [Added title page title]
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Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Summary: In this thesis, an adaptive ring amplifier is proposed to introduce a degree of freedom in speed/stabilization design trade-off in the original ring amplifier. It also introduces an area efficient solution for the auto-zeroing stability problem that the conventional ring amplifier suffers from. The proposed adaptive ring amplifier improves the linearity by 10dB at the same operating frequency. Moreover, it achieves a 40% improvement in the operating frequency for the same linearity and settling requirements. It has a 98% area reduction compared to the conventional ring amplifier for the same stability conditions. A 12-bit 25MS/s SAR-Assisted two-stage pipeline ADC is designed and implemented in a low-cost 0.13om CMOS technology. It consists of a 6-bit first stage followed by a 7-bit second stage utilizing the proposed adaptive ring amplifier in order to meet the stringent specifications. In addition, a detect-and-skip (DAS) capacitive DAC (CDAC) switching method is used to reduce the switching energy of the first-stage CDAC. The ADC consumes 0.89mW achieving a Figure of Merit (FoM) of 13.7 fJ/conversion-step while operating from a single 1.2V supply
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Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2016.Ka.A (Browse shelf(Opens below)) Not for loan 01010110070665000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2016.Ka.A (Browse shelf(Opens below)) 70665.CD Not for loan 01020110070665000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

In this thesis, an adaptive ring amplifier is proposed to introduce a degree of freedom in speed/stabilization design trade-off in the original ring amplifier. It also introduces an area efficient solution for the auto-zeroing stability problem that the conventional ring amplifier suffers from. The proposed adaptive ring amplifier improves the linearity by 10dB at the same operating frequency. Moreover, it achieves a 40% improvement in the operating frequency for the same linearity and settling requirements. It has a 98% area reduction compared to the conventional ring amplifier for the same stability conditions. A 12-bit 25MS/s SAR-Assisted two-stage pipeline ADC is designed and implemented in a low-cost 0.13om CMOS technology. It consists of a 6-bit first stage followed by a 7-bit second stage utilizing the proposed adaptive ring amplifier in order to meet the stringent specifications. In addition, a detect-and-skip (DAS) capacitive DAC (CDAC) switching method is used to reduce the switching energy of the first-stage CDAC. The ADC consumes 0.89mW achieving a Figure of Merit (FoM) of 13.7 fJ/conversion-step while operating from a single 1.2V supply

Issued also as CD

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