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A low complexity fast fourier transform architecture / Ahmed Mamdouh Ahmed Elsha{uFB01}y ; Supervised Omar Ahmed Ali Nasr

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Ahmed Mamdouh Ahmed Elsha{uFB01}y , 2016Description: 94 P. : charts , facsimiles ; 30cmOther title:
  • بنية تحويلة فورير السريعة ذات التعقيد البسيط [Added title page title]
Subject(s): Online resources: Available additional physical forms:
  • Issued also as CD
Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Summary: In digital signal processing {uFB01}eld, it is often required to transform the signal between time and frequency domains using the fast fourier transform (FFT) algorithm. Therefore FFT blocks is one of the basic building block in digital signal processors. The basic computational units of the high-throughput pipeline FFT architectures are the butter{uFB02}y block and a rotator block. The butter{uFB02}y block performs a weighted complex addition and subtraction, while the rotator block performs a rotation in the complex plane by a given rotation angles, i.e., the twiddle factors. Compared to the butter{uFB02}y operation, the rotator operation is the costly one. In this work we propose a restructure to the conventional FFT rotational angles into a modi{uFB01}ed hardWare friendly FFT (HW-F FFT) angles. The main goal is to enhance either power, area or speed performance while maintaining the signal to Quantization Noise Ratio (SQNR) requirements
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Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2016.Ah.L (Browse shelf(Opens below)) Not for loan 01010110071261000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2016.Ah.L (Browse shelf(Opens below)) 71261.CD Not for loan 01020110071261000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

In digital signal processing {uFB01}eld, it is often required to transform the signal between time and frequency domains using the fast fourier transform (FFT) algorithm. Therefore FFT blocks is one of the basic building block in digital signal processors. The basic computational units of the high-throughput pipeline FFT architectures are the butter{uFB02}y block and a rotator block. The butter{uFB02}y block performs a weighted complex addition and subtraction, while the rotator block performs a rotation in the complex plane by a given rotation angles, i.e., the twiddle factors. Compared to the butter{uFB02}y operation, the rotator operation is the costly one. In this work we propose a restructure to the conventional FFT rotational angles into a modi{uFB01}ed hardWare friendly FFT (HW-F FFT) angles. The main goal is to enhance either power, area or speed performance while maintaining the signal to Quantization Noise Ratio (SQNR) requirements

Issued also as CD

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