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Design of frequency based analog to digital converter (FADC) : new design methodology for voltage-to-frequency-converter (VFC) circuits / Mohammed Ahmed Ahmed Mahmoud Elgabry ; Supervised Ahmed M. Soliman , Hassan Mostafa

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Mohammed Ahmed Ahmed Mahmoud Elgabry , 2017Description: 82 P. : charts , facsimiles ; 30cmOther title:
  • تصميم محول تناظري رقمي معتمد على صيغة التردد : طريقة تصميم جديدة لدوائر تحويل الجهد الى تردد [Added title page title]
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  • Issued also as CD
Dissertation note: Thesis (M.Sc.) - Cairo University -Faculty of Engineering - Department of Electronics and Communications Engineering Summary: In this thesis we introduce a new design methodology for Voltage-to-Frequency Converters (VFCs) circuits suitable for Time-Based Analog-to-Digital Converters (T-ADCs) circuits. This new methodology is tested using the parasitic after post layout using Cadence based on TSMC 65nm CMOS technology
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Item type Current library Home library Call number Copy number Status Date due Barcode
Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2017.Mo.D (Browse shelf(Opens below)) Not for loan 01010110074237000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2017.Mo.D (Browse shelf(Opens below)) 74237.CD Not for loan 01020110074237000

Thesis (M.Sc.) - Cairo University -Faculty of Engineering - Department of Electronics and Communications Engineering

In this thesis we introduce a new design methodology for Voltage-to-Frequency Converters (VFCs) circuits suitable for Time-Based Analog-to-Digital Converters (T-ADCs) circuits. This new methodology is tested using the parasitic after post layout using Cadence based on TSMC 65nm CMOS technology

Issued also as CD

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