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Continuous-time sigma-delta modulator using a novel ring amplifier architecture / Amr Ahmed Saad Ahmed ; Supervised Ahmed Nader Mohieldin , Mohamed M. Aboudina , Faisal A. Hussien

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Amr Ahmed Saad Ahmed , 2018Description: 97 P. : charts , facsimiles ; 25cmOther title:
  • معدل سيجما دلتا مستمر الوقت باستخدام اسلوب بناء جديد للمكبر الحلقي [Added title page title]
Subject(s): Online resources: Available additional physical forms:
  • Issued also as CD
Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Summary: In this thesis a novel ring amplifier architecture is proposed. This structure is the first of its kind in which it enables the usage of ring amplifier in continuous time applications. The new structure design and design equations is clarified with the help of a design example of second order continuous time modulator. Then, the proposed architecture is used to implement a more complex third order, 1.5 bit quantizer V4 modulator. The modulator is implemented in a 65nm CMOS technology and can achieves a SNDR of 66 dB for a 5 MHz BW input signal while consuming only 1.5 mW from a 0.9 V single supply. Hence, achieving a Figure of Merit (FoM) of 92 fJ/Conv
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Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2018.Am.C (Browse shelf(Opens below)) Not for loan 01010110077115000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2018.Am.C (Browse shelf(Opens below)) 77115.CD Not for loan 01020110077115000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

In this thesis a novel ring amplifier architecture is proposed. This structure is the first of its kind in which it enables the usage of ring amplifier in continuous time applications. The new structure design and design equations is clarified with the help of a design example of second order continuous time modulator. Then, the proposed architecture is used to implement a more complex third order, 1.5 bit quantizer V4 modulator. The modulator is implemented in a 65nm CMOS technology and can achieves a SNDR of 66 dB for a 5 MHz BW input signal while consuming only 1.5 mW from a 0.9 V single supply. Hence, achieving a Figure of Merit (FoM) of 92 fJ/Conv

Issued also as CD

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