Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows a portion of the logic to be reconfigured at runtime while the rest of the logic keeps operating. Such category of designs called Dynamically Reconfigurable Systems (DRS) designs. This feature enables the designers to build complex systems such as Software Defined Radio (SDR) in a reasonable area. Despite of the flexibility provided by the DPR, there are new challenges to design and verify the designs which utilize the DPR technique when it is compared to static FPGA systems. In this thesis, a new verification methodology for DPR is presented. The new methodology addresses DPR specific logic and issues such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. This DPR logic is verified using Assertion Based Verification (ABV) by modeling its functionality using System Verilog Assertion (SVA) properties, then instrument the design with these properties. Following that, these properties are verified using simulation or formal methods to check the correctness of the DPR logic. Also, this thesis presents an automated flow for Clock Domain Crossings (CDC) verification for DRS designs

Issued also as CD