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Power-efficient design of high performance googlenet-based convolutional neural networks hardware accelerator / Ahmed Jamal Mohamed Abdelmaksoud ; Supervised Ahmed Hussien Mohamed , Hassan Mostafa Hassan

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Ahmed Jamal Mohamed Abdelmaksoud , 2021Description: 74 P. : charts , facsimiles ; 30cmOther title:
  • تصميم موفر للطاقة لمسرع الشبكات العصبية التلاففية عالي الأداء [Added title page title]
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Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Summary: Convolutional neural networks (CNNs) have dominated image recognition and object detection models in the last few years. However, they require a huge cost of computation and a large memory size.This thesis presents a low-power convolutional neural networks hardware accelerator based on GoogLeNet.Several optimization and approximation techniques are applied to reduce the power consumption and memory size.Consequently, only FPGA BRAMs are used for weights storage without using offline DRAMs. In addition, the proposed hardware accelerator uses zero DSP units.The accelerator classifies 25.1 frames/sec with only 3.92W, which is more power-efficient than previous GoogLeNet FPGA implementations.The processor uses only 224 parallel elements (PEs) and achieves an average classification efficiency of 91%
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Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2021.Ah.P (Browse shelf(Opens below)) Not for loan 01010110085524000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2021.Ah.P (Browse shelf(Opens below)) 85524.CD Not for loan 01020110085524000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

Convolutional neural networks (CNNs) have dominated image recognition and object detection models in the last few years. However, they require a huge cost of computation and a large memory size.This thesis presents a low-power convolutional neural networks hardware accelerator based on GoogLeNet.Several optimization and approximation techniques are applied to reduce the power consumption and memory size.Consequently, only FPGA BRAMs are used for weights storage without using offline DRAMs. In addition, the proposed hardware accelerator uses zero DSP units.The accelerator classifies 25.1 frames/sec with only 3.92W, which is more power-efficient than previous GoogLeNet FPGA implementations.The processor uses only 224 parallel elements (PEs) and achieves an average classification efficiency of 91%

Issued also as CD

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