Study and Realization Of RSA Algorithm Using FPGA / Ghada Farouk Naiem Elsaid Kdr ; Supervised Aly Ezat Salama , Amr Yossef
Language: Eng Publication details: Cairo : Ghada Farouk Naiem Elsaid Kdr , 2004Description: 125p : ill ; 30cmOther title:- دراسة و تحقيق خوارزميRSAباستخدام مصفوفة البوابات المبرمجة حقليا [Added title page title]
- Issued also as CD
Item type | Current library | Home library | Call number | Status | Date due | Barcode | |
---|---|---|---|---|---|---|---|
Thesis | قاعة الرسائل الجامعية - الدور الاول | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2004.Gh.S (Browse shelf(Opens below)) | Not for loan | 01010110043420000 | ||
CD - Rom | مخـــزن الرســائل الجـــامعية - البدروم | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2004.Gh.S (Browse shelf(Opens below)) | Not for loan | 01020110043420000 |
Browsing المكتبة المركزبة الجديدة - جامعة القاهرة shelves Close shelf browser (Hides shelf browser)
No cover image available | No cover image available | No cover image available | No cover image available | No cover image available | No cover image available | No cover image available | ||
Cai01.13.08.M.Sc.2004.Ah.M Multilayered Space - Frequency Coding for OFDM System / | Cai01.13.08.M.Sc.2004.Am.N A novel dual variable step size blind equalizer / | Cai01.13.08.M.Sc.2004.Am.N A novel dual variable step size blind equalizer / | Cai01.13.08.M.Sc.2004.Gh.S Study and Realization Of RSA Algorithm Using FPGA / | Cai01.13.08.M.Sc.2004.Gh.S Study and Realization Of RSA Algorithm Using FPGA / | Cai01.13.08.M.Sc.2004.Ha.N A new enhanced ipsec hybrid model using aes / | Cai01.13.08.M.Sc.2004.Ha.N A new enhanced ipsec hybrid model using aes / |
Thesis (M.Sc.) - Cairo University - Faculty Of Engineering - Department Of Electronics and Communications
In this thesis we present a hardware implementation of the RSA algorithm for public - key cryptographyThe RSA algorithm requires the computation of modular exponentials on large integers that can be reduced to repeated modular multiplicationsWe present a serial - parallel implementation of RSA , which is based upon the Montgomery algorithmThe proposed architecture is configurable and scalable , and it exploits specific capabilities of programmable devicesThe final performance level is a function of the word length and serialization factorWe provide a thorough discussion of design tradeoffs in terms of area requirements vsperformance for different values of the key length , the word length and serialization factor
Issued also as CD
There are no comments on this title.