TY  - BOOK
AU  - Khallid Hussien Mahmoud Khallaf
AU  - Abdelhalim Shousha , Ahmed Tarek Sayed 
AU  - Ahmed Tarek Sayed , 
TI  - Low power high speed digital arithmetic circuit / 
PY  - 2010///
CY  - Cairo : 
PB  - Khallid Hussien Mahmoud Khallaf , 
KW  - Full adder
KW  - Low power
KW  - Power consumption
N1  - Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication; Issued also as CD
N2  - We explored the main building block of most arithmetic digital circuits viz . The full adder . We surveyed the most recent published full adder cells . We designed them simulated and measured their power consumption and delays . We identified key sub-circuits that are critical to power consumption
UR  - http://172.23.153.220/th.pdf
ER  -