Amr Abdelfatah Ramdan Sayed Ahmed <br/><br/>
Verification of decimal floating-point operations /  
 التحقق من صحة العمليات الحسابية العشرية 
Amr Abdelfatah Ramdan Sayed Ahmed ; Supervised Hossam A. H. Fahmy 
 - Cairo :   Amr Abdelfatah Ramdan Sayed Ahmed ,   2011 
 - 98 P. ;   30cm 
<br/><br/>Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication 
<br/><br/> Decimal floating-point designs require a verification process to prove that the design is in compliance with the IEEE standarf for floating-point arihmetic (IEEE Std 754-2008). Our work is a decimal floating-point verification using simulation based verification, which a simulation method based on coverage models to cover corner cases of a certain decimal floating-point operation 
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<br/><br/><label>Subjects--Index Terms: </label>Decimal floating-point operations Simulation based verification Test vectors