Identifying worst - case test vectors for leakage current and delay failures induced by total dose in CMOS ASIC /
عند تعرضها للآشعاع CMOS تحديد حالات الاختبارات التى تؤدى الى اسوأ تسريب فى التيار الكهربائى و اخطاء التاخير للدوائر المتكاملة التى تستخدم تكنولوجيا ال
Mostafa Mahmoud Abdelaziz Mohamed ; Supervised Ihab Elsyaed Talkhan , Amr Galal Eldin Ahmed Wassal
- Cairo : Mostafa Mahmoud Abdelaziz Mohamed , 2014
- 70 P. : charts ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Computer Engineering
The test standard MIL - STD-883, method 1019, for testing electronic devices exposed to total - ionizing dose (TID) emphasizes the use of worst - case test - vectors (WCTV). However, they are typically not used in the total - dose testing of ASIC devices because they are known to be very difficult to identify. In the TID testing for space application, WCTV can be used to test the hardness assurance of a certain ASIC part before using it in space. This thesis discusses the development of novel methodologies which successfully identify, for the first time, the worst-case test-vectors for CMOS sequential ASIC devices targeting both leakage current failures, logic failures and delay failures induced by total-ionizing dose (TID). Those methodologies follow the typical design flow of ASIC device using standard - cell libraries. To identify the WCTV, we started by developing a cell-level fault model for each type of failure induced by total dose for all cells within a given standard - cell library. The fault models are implemented using a hardware descriptive language (HDL) and validated using SPICE simulations in where we use TID degraded MOS parameters