TY  - BOOK
AU  - Ezz Eldin Omar Ahmed Hussein Hamed 
AU  - Hanan A. Kamal  , 
AU  - Serag E. D. Habib , 
TI  - Asic design of all digital pll{u2019}s for processors-clock generation / 
PY  - 2012///
CY  - Cairo : 
PB  - Ezz Eldin Omar Ahmed Hussein Hamed  , 
KW  - ADPLL
KW  - Bang-Bang
KW  - Synthesizable PLL
N1  - Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication; Issued also as CD
N2  - All Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks  mainly to their scalability across technology nodes. This work presents a new  standard-cell based ADPLL for processors{u2019} clock generation. The target technology is  TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800  MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total  power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These  features make the proposed ADPLL design very suitable for SoC applications
UR  - http://172.23.153.220/th.pdf
ER  -