TY  - BOOK
AU  - Mervat Mohamed Adel Mahmoud
AU  - Dalia A. Eldib , 
AU  - Hossam A. H. Fahmy , 
TI  - Low energy computer architecture designs / 
PY  - 2019///
CY  - Cairo : 
PB  - Mervat Mohamed Adel Mahmoud , 
KW  - Low energy
KW  - Parallel architectures
KW  - Pipeline processing
N1  - Thesis (Ph.D.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication; Issued also as CD
N2  - The continuous increase in chip integration and the associated energy consumption concerns made low power/energy design one of the main challenges facing VLSI systems. A low energy clock-gated pipelined dual base binary/decimal fixed-point multiplier is suggested extending a previously proposed non-pipelined design. A thorough study conducted on both the pipelined and non-pipelined designs versus other architectures in literature proves tremendous reductions in power, energy and area consumption.In addition, a new low energy lossless compression/decompression approach is suggested for main memory data. The proposed design lowers energy consumption due to its simplicity and low latency
UR  - http://172.23.153.220/th.pdf
ER  -