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High throughput low power architecture for network-on-chip / Mohamed Ahmed Abdelghany Ahmed Elsayed Salem ; Supervised Darek Korzec , Mohammed Ismail

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Mohamed Ahmed Abdelghany Ahmed Elsayed Salem , 2010Description: 159Leaves : charts , facsimiles ; 30cmOther title:
  • تصميم ذو معدل مرتفع لانتقال البيانات ومنخفض لاستهلاك الطاقة للشبكة الرقاقة الالكترونية [Added title page title]
Online resources: Dissertation note: Thesis (Ph.D.) - German University - Faculty of Postgraduate Studies and Scientific Research - Department of Information Engineering and Technology Summary: With the rapid advance in technology in today's System - on - chip (SoC) , the number and functionality of intellectual property blocks (IPs) and the complexity of interconnects have been increasing dramatically . Since the system scalability and bandwidth of SoCs are limited , Network on Chip (NoC) architectures are emerging as the best replacement for the existing interconnects architectures
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Thesis Thesis قاعة الثقاقات الاجنبية - الدور الثالث المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.34.Ph.D.2010.Mo.H (Browse shelf(Opens below)) Not for loan 01010110060184000

Thesis (Ph.D.) - German University - Faculty of Postgraduate Studies and Scientific Research - Department of Information Engineering and Technology

With the rapid advance in technology in today's System - on - chip (SoC) , the number and functionality of intellectual property blocks (IPs) and the complexity of interconnects have been increasing dramatically . Since the system scalability and bandwidth of SoCs are limited , Network on Chip (NoC) architectures are emerging as the best replacement for the existing interconnects architectures

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