A pipeline adc using enhanced-linearity ring-amplifier / Ahmed Gharib Abdelraouf Ahmed Gadelkarim ; Supervised Ahmed Nader Mohieldin , Mohamed Mostafa Aboudina
Material type: TextLanguage: English Publication details: Cairo : Ahmed Gharib Abdelraouf Ahmed Gadelkarim , 2020Description: 67 P. : charts , facsimiles ; 30cmOther title:- محول بيانات تناظرى الى رقمى بتقنية الانبوبة بأستخدام مكبر حلقى محسًن الصفة الخطية [Added title page title]
- Issued also as CD
Item type | Current library | Home library | Call number | Copy number | Status | Date due | Barcode | |
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Thesis | قاعة الرسائل الجامعية - الدور الاول | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2020.Ah.P (Browse shelf(Opens below)) | Not for loan | 01010110083204000 | |||
CD - Rom | مخـــزن الرســائل الجـــامعية - البدروم | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2020.Ah.P (Browse shelf(Opens below)) | 83204.CD | Not for loan | 01020110083204000 |
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
This thesis proposes a slew rate enhancement technique which solves the fundamental trade-off between speed and stability. The proposal is to use a rail-to-rail controlled feedforward path to be used in parallel with an original ring amplifier. This feedforward path boosts the linearity of the amplifier significantly without any stability degradation.The linearity improvement is achieved by enhancing the slew rate of the used amplifier while minimizing the overhead current consumption. Thus, using this feedforward path enhances the linearity for almost the same current consumption, hence reducing the overall system figure of merit (FoM). The core idea of the thesis has been verified using M-DAC architecture with unity closed loop gain. The proposal enhances the total harmonic distortion by 10dB while reducing the overall FoM by more than half compared to state-of-the-art techniques. Then, a 10-bit 1.5-bit/stage pipeline ADC has been implemented using this adaptive ring-amplifier.The full system has been implemented using TSMC 65nm CMOS technology and 0.9V supply voltage
Issued also as CD
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