Low power high speed digital arithmetic circuit / Khallid Hussien Mahmoud Khallaf ; Supervised Abdelhalim Shousha , Ahmed Tarek Sayed
Material type:
- الدوائر الحسابية الرقمية منخفضة القدرة عالية السرعة [Added title page title]
- Issued also as CD
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قاعة الرسائل الجامعية - الدور الاول | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2010.Kh.L (Browse shelf(Opens below)) | Not for loan | 01010110054128000 | ||
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مخـــزن الرســائل الجـــامعية - البدروم | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2010.Kh.L (Browse shelf(Opens below)) | 54128.CD | Not for loan | 01020110054128000 |
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
We explored the main building block of most arithmetic digital circuits viz . The full adder . We surveyed the most recent published full adder cells . We designed them simulated and measured their power consumption and delays . We identified key sub-circuits that are critical to power consumption
Issued also as CD
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