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Design for yield for sub-22nm FinFET-based FPGA / Mohamed Mohie Eldin Mohamed Aly Hassan ; Supervised Hossam A. H. Fahmy , Hassan Mostafa

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Mohamed Mohie Eldin Mohamed Aly Hassan , 2017Description: 75 P. : photographs plans ; 30cmOther title:
  • أبعاد أصغر من٢٢ نانومتر بكفائة عالية ضد عيوب التصنيع FinFET تصميم دوائر مصفوفات البوابات القابلة للبرمجة بإستخدام تكنولوجيا [Added title page title]
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Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Summary: In this thesis, a performance evaluation study for a FinFET-Based FPGA cluster under threshold voltage variation, representing the Die-to-Die variations, is launched with technology scaling starting from 20nm down to 7nm nodes showing the scaling trends of various performance metrics including the average power, delay, and power-delay product. Also some design insights and recommendations are proposed for the designers to achieve yield percentage of 99.87%. The leakage power is also studied for 14nm technology node under threshold voltage and temperature variations. Some solutions are implemented for leakage power control under threshold voltage variations including transistor stacking, minimum leakage vector, and gate sizing
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Item type Current library Home library Call number Copy number Status Date due Barcode
Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2017.Mo.D (Browse shelf(Opens below)) Not for loan 01010110073450000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2017.Mo.D (Browse shelf(Opens below)) 73450.CD Not for loan 01020110073450000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

In this thesis, a performance evaluation study for a FinFET-Based FPGA cluster under threshold voltage variation, representing the Die-to-Die variations, is launched with technology scaling starting from 20nm down to 7nm nodes showing the scaling trends of various performance metrics including the average power, delay, and power-delay product. Also some design insights and recommendations are proposed for the designers to achieve yield percentage of 99.87%. The leakage power is also studied for 14nm technology node under threshold voltage and temperature variations. Some solutions are implemented for leakage power control under threshold voltage variations including transistor stacking, minimum leakage vector, and gate sizing

Issued also as CD

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