| 000 | 015940000a22003370004500 | ||
|---|---|---|---|
| 003 | EG-GICUC | ||
| 005 | 20250223025503.0 | ||
| 008 | 081019s2008 ua e f m 000 0 eng d | ||
| 040 |
_aEG-GICUC _beng _cEG-GICUC |
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| 041 | 0 | _aEng | |
| 049 | _aDeposite | ||
| 097 | _aM.Sc | ||
| 099 | _aCai01.13.08.M.Sc.2008.Mo.A | ||
| 100 | 0 | _aMohamed Gamal Eldin Ahmed Egila | |
| 245 | 1 | 0 |
_aASIC implementation of an all digital delay locked loop ADDLL / _cMohamed Gamal Eldin Ahmed Egila ; Supervised Serag Eldin Habib , Nivin Abuelhadid |
| 246 | 1 | 5 | _aتصميم دائرة متكاملة لحلقة رقمية بالكامل لضبط التأخير |
| 260 |
_aCairo : _bMohamed Gamal Eldin Ahmed Egila , _c2008 |
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| 300 |
_a68P. : _bplans ; _c30cm |
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| 502 | _aThesis (M.Sc.) - Cairo University - Faculty Of Engineering - Department Of Electronics and Communications | ||
| 520 | _aClock recovery circuits are basic components in today's VLSI circuits.Delay locked loops (DLLs) are attractive solutions for clock recovery due to their stability , low latency and the absence of phase error accumulation.All digital DLLs (ADDLL) have the added advantage of simple design and compatibility with mainstream digital design flows | ||
| 530 | _aIssued also as CD | ||
| 653 | 4 | _aAll digital delay lock loops | |
| 653 | 4 | _aDelay locked loops | |
| 653 | 4 | _aDLL | |
| 700 | 0 |
_aNivin Abuelhadid , _eSupervisor |
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| 700 | 0 |
_aSerag Eldin Elsayed Habib , _eSupervisor |
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| 856 | _uhttp://172.23.153.220/th.pdf | ||
| 905 |
_aEnas _eCataloger |
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| 905 |
_aMustafa _eRevisor |
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| 942 |
_2ddc _cTH |
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| 999 |
_c14059 _d14059 |
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