000 01555cam a2200337 a 4500
003 EG-GiCUC
005 20250223030311.0
008 101024s2010 ua dh f m 000 0 eng d
040 _aEG-GiCUC
_beng
_cEG-GiCUC
041 0 _aeng
049 _aDeposite
097 _aM.Sc
099 _aCai01.13.08.M.Sc.2010.Kh.L
100 0 _aKhallid Hussien Mahmoud Khallaf
245 1 0 _aLow power high speed digital arithmetic circuit /
_cKhallid Hussien Mahmoud Khallaf ; Supervised Abdelhalim Shousha , Ahmed Tarek Sayed
246 1 5 _aالدوائر الحسابية الرقمية منخفضة القدرة عالية السرعة
260 _aCairo :
_bKhallid Hussien Mahmoud Khallaf ,
_c2010
300 _a78 P. :
_bcharts , facsimiles ;
_c30cm
502 _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
520 _aWe explored the main building block of most arithmetic digital circuits viz . The full adder . We surveyed the most recent published full adder cells . We designed them simulated and measured their power consumption and delays . We identified key sub-circuits that are critical to power consumption
530 _aIssued also as CD
653 4 _aFull adder
653 4 _aLow power
653 4 _aPower consumption
700 0 _aAbdelhalim Shousha , Ahmed Tarek Sayed
_eSupervisor
700 0 _aAhmed Tarek Sayed ,
_eSupervisor
856 _uhttp://172.23.153.220/th.pdf
905 _aNazla
_eRevisor
905 _aSoheir
_eCataloger
942 _2ddc
_cTH
999 _c31841
_d31841