000 01550cam a2200325 a 4500
003 EG-GiCUC
005 20250223030522.0
008 111130s2011 ua f m 000 0 eng d
040 _aEG-GiCUC
_beng
_cEG-GiCUC
041 0 _aeng
049 _aDeposite
097 _aM.Sc
099 _aCai01.13.08.M.Sc.2011.Am.V
100 0 _aAmr Abdelfatah Ramdan Sayed Ahmed
245 1 0 _aVerification of decimal floating-point operations /
_cAmr Abdelfatah Ramdan Sayed Ahmed ; Supervised Hossam A. H. Fahmy
246 1 5 _aالتحقق من صحة العمليات الحسابية العشرية
260 _aCairo :
_bAmr Abdelfatah Ramdan Sayed Ahmed ,
_c2011
300 _a98 P. ;
_c30cm
502 _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
520 _aDecimal floating-point designs require a verification process to prove that the design is in compliance with the IEEE standarf for floating-point arihmetic (IEEE Std 754-2008). Our work is a decimal floating-point verification using simulation based verification, which a simulation method based on coverage models to cover corner cases of a certain decimal floating-point operation
530 _aIssued also as CD
653 4 _aDecimal floating-point operations
653 4 _aSimulation based verification
653 4 _aTest vectors
700 0 _aHossam Aly Hassan Fahmy ,
_eSupervisor
856 _uhttp://172.23.153.220/th.pdf
905 _aNazla
_eRevisor
905 _aSamia
_eCataloger
942 _2ddc
_cTH
999 _c36403
_d36403