| 000 | 01824cam a2200337 a 4500 | ||
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| 003 | EG-GiCUC | ||
| 005 | 20250223031202.0 | ||
| 008 | 150326s2012 ua h f m 000 0 eng d | ||
| 040 |
_aEG-GiCUC _beng _cEG-GiCUC |
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| 041 | 0 | _aeng | |
| 049 | _aDeposite | ||
| 097 | _aM.Sc | ||
| 099 | _aCai01.13.08.M.Sc.2012.Ez.A | ||
| 100 | 0 | _aEzz Eldin Omar Ahmed Hussein Hamed | |
| 245 | 1 | 0 |
_aAsic design of all digital pll{u2019}s for processors-clock generation / _cEzzeldin Omar Ahmed Hussein Hamed ; Supervised Serag E. D. Habib , Hanan A. Kamal |
| 246 | 1 | 5 | _aتصميم دائرة رقمية بالكامل لضبط طور إشارة الساعة لمشغل دقيق |
| 260 |
_aCairo : _bEzz Eldin Omar Ahmed Hussein Hamed , _c2012 |
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| 300 |
_a61 P. : _bfacsimiles ; _c30cm |
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| 502 | _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication | ||
| 520 | _aAll Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks mainly to their scalability across technology nodes. This work presents a new standard-cell based ADPLL for processors{u2019} clock generation. The target technology is TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800 MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These features make the proposed ADPLL design very suitable for SoC applications | ||
| 530 | _aIssued also as CD | ||
| 653 | 4 | _aADPLL | |
| 653 | 4 | _aBang-Bang | |
| 653 | 4 | _aSynthesizable PLL | |
| 700 | 0 |
_aHanan A. Kamal , _eSupervisor |
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| 700 | 0 |
_aSerag E. D. Habib , _eSupervisor |
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| 856 | _uhttp://172.23.153.220/th.pdf | ||
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_aAml _eCataloger |
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_aNazla _eRevisor |
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_2ddc _cTH |
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_c50066 _d50066 |
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