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040 _aEG-GiCUC
_beng
_cEG-GiCUC
041 0 _aeng
049 _aDeposite
097 _aM.Sc
099 _aCai01.13.08.M.Sc.2015.Mo.D
100 0 _aMohamed Radwan Hassan Abdelhamid
245 1 0 _aDesign techniques for low-power high-speed pipelined analog to digital converters /
_cMohamed Radwan Hassan Abdelhamid ; Supervised Ahmed Nader Mohi Eldin , Mohamed M. Aboudina , Faisal A. Hussien
246 1 5 _aتقنيات التصميم قليلة القدرة وعالية السرعة لمحولات البيانات التناظرية للرقمية بتقنية أنبوبة المراحل المتتالية
260 _aCairo :
_bMohamed Radwan Hassan Abdelhamid ,
_c2015
300 _a74 P. :
_bfacsimiles , charts ;
_c30cm
502 _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Engineering
520 _aIn this thesis, design techniques are proposed for Analog to Digital converters, which are the core of the analog front end of wireless transceivers. Current wireless communications standards dictate a low-power high-speed circuit design. Two switched-capacitor techniques are proposed to achieve high precision despite the finite gain of operational amplifiers (opamps). Predict and Level Shift technique is proposed to enhance the effective gain of opamps through predicting the output during the sampling phase of the Analog to Digital Converter without incurring extra clock phases. Charge-compensated Correlated Level shifting technique is proposed to improve the effective gain through using single-stage opamps for high-speed and resolution. An 11-bit 200MS/s pipelined ADC is designed through utilizing CC-CLS in the first stages. The ADC consumes 26 mW achieving a Figure of Merit of 73 fJ/conversion step in 130nm CMOS technology
530 _aIssued also as CD
653 4 _aAnalog to Digital Converter
653 4 _aCorrelated Level Shifting
653 4 _aPipelined ADC
700 0 _aAhmed Nader Mohi Eldin ,
_eSupervisor
700 0 _aFaisal A. Hussien ,
_eSupervisor
700 0 _aMohamed M. Aboudina ,
_eSupervisor
856 _uhttp://172.23.153.220/th.pdf
905 _aAml
_eCataloger
905 _aNazla
_eRevisor
942 _2ddc
_cTH
999 _c54618
_d54618