000 02297cam a2200337 a 4500
003 EG-GiCUC
005 20250223031639.0
008 170116s2016 ua dh f m 000 0 eng d
040 _aEG-GiCUC
_beng
_cEG-GiCUC
041 0 _aeng
049 _aDeposite
097 _aM.Sc
099 _aCai01.13.08.M.Sc.2016.Al.U
100 0 _aAli Ahmed Seddeek Mohamed Farid
245 1 0 _aUltra low power sar adc for sensor nodes /
_cAli Ahmed Seddeek Mohamed Farid ; Supervised Ahmed Ahmed Emira , Mohamed Mostafa Aboudina
246 1 5 _aمحولات الب{u٠٦أأ}انات ذات الطاقة المنخفضة لعقد الاستشعار
260 _aCairo :
_bAli Ahmed Seddeek Mohamed Farid ,
_c2016
300 _a95 P. :
_bcharts , facsimiles ;
_c30cm
502 _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
520 _aA new charge redistribution technique for CDAC based SAR ADC, with an input dynamic range equals to twice the reference voltage for single ended applications. Compared to SAR converters using conventional switching techniques, the proposed solution reduces the capacitive digital-to-analog (CDAC) average switching energy and total capacitive area by 78.2% and 50%, respectively. Moreover, the Di{uFB00}erential Non-Linearity (DNL) and Integral Non-Linearity (INL) are improved by factor of two compared to the conventional approaches. A new two stages dynamic comparator architecture is introduced to minimize the hysteresis e{uFB00}ect and help in improving the overall linearity. A prototype was fabricated using TSMC 65nm CMOS technology and it occupies an active area of 0.039mm2. The ADC achieves an SNDR of 62dB for an input voltage amplitude of 1.5Vp and frequency of 100kHz. The ADC consumes 5uA at 1MS/s resulting in a {uFB01}gure of merit (FOM) of 11-fJ/conversion step
530 _aIssued also as CD
653 4 _aAnalog-to-Digital converters
653 4 _aDouble reference voltage dynamic range
653 4 _aSuccessive approximation registers
700 0 _aAhmed Ahmed Emira ,
_eSupervisor
700 0 _aMohamed Mostafa Aboudina ,
_eSupervisor
856 _uhttp://172.23.153.220/th.pdf
905 _aNazla
_eRevisor
905 _aSoheir
_eCataloger
942 _2ddc
_cTH
999 _c59448
_d59448