000			02304cam a2200337 a 4500
003			EG-GiCUC
005			20250223031654.0
008			170226s2016 ua f m 000 0 eng d
040			_aEG-GiCUC _beng _cEG-GiCUC
041	0		_aeng
049			_aDeposite
097			_aM.Sc
099			_aCai01.13.08.M.Sc.2016.Ah.S
100	0		_aAhmed Mohamed Abdelmawgoud Ragab
245	1	2	_aA single core fpga aes cipher\decipher for key lengths of 128, 192 and 256 bits / _cAhmed Mohamed Abdelmawgoud Ragab ; Supervised Ahmed H. Khalil , Hisham M. Hamed
246	1	5	_aلأطوال المفاتيح192:128و 256 بت AES تحقيق نظام تشفير/ فك تشفيرٍعلى دائرة منطقية قابلة للبرمجة بنواة واحدة للنظام
260			_aCairo : _bAhmed Mohamed Abdelmawgoud Ragab , _c2016
300			_a109 P. ; _c30cm
502			_aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
520			_aThis work present an optimized pipelined hardware implementation of the advanced encryption standard (AES) with key lengths of 128, 192 and 256 bits on an altera stratix III-EP3SL150F1152 field programmable gate array (FPGA). Starting from an architecture dedicated to 256-bit key operations, a series of optimization are performed to allow the handling of 128-bit and 192-bit keys, using one core, rather than three separate cores. The various operations required for the AES algorithm are thus analyzed from a hardware implementation perspective. The system throughput is also enhanced through the simultaneous calculations of operations. In the timing report, the system frequency reaches a maximum of 332 MHz producing a maximum throughput of 42.48 Gbps with a latency ranges from 21 to 29 clk cycles depending on the selected operation. The design was tested on a terasic DE3-150 development board at 100 MHZ, and operated with the Altera-NiosII CPU environment
530			_aIssued also as CD
653		4	_aAES
653		4	_aFPGA
653		4	_aOperations sharing
700	0		_aAhmed Hussein Khalil , _eSupervisor
700	0		_aHisham Mohamed Fathy Hamed , _eSupervisor
856			_uhttp://172.23.153.220/th.pdf
905			_aNazla _eRevisor
905			_aSamia _eCataloger
942			_2ddc _cTH
999			_c59985 _d59985