| 000 | 02025cam a2200349 a 4500 | ||
|---|---|---|---|
| 003 | EG-GiCUC | ||
| 005 | 20250223032203.0 | ||
| 008 | 190210s2018 ua dh f m 000 0 eng d | ||
| 040 |
_aEG-GiCUC _beng _cEG-GiCUC |
||
| 041 | 0 | _aeng | |
| 049 | _aDeposite | ||
| 097 | _aM.Sc | ||
| 099 | _aCai01.13.08.M.Sc.2018.Am.C | ||
| 100 | 0 | _aAmr Ahmed Saad Ahmed | |
| 245 | 1 | 0 |
_aContinuous-time sigma-delta modulator using a novel ring amplifier architecture / _cAmr Ahmed Saad Ahmed ; Supervised Ahmed Nader Mohieldin , Mohamed M. Aboudina , Faisal A. Hussien |
| 246 | 1 | 5 | _aمعدل سيجما دلتا مستمر الوقت باستخدام اسلوب بناء جديد للمكبر الحلقي |
| 260 |
_aCairo : _bAmr Ahmed Saad Ahmed , _c2018 |
||
| 300 |
_a97 P. : _bcharts , facsimiles ; _c25cm |
||
| 502 | _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications | ||
| 520 | _aIn this thesis a novel ring amplifier architecture is proposed. This structure is the first of its kind in which it enables the usage of ring amplifier in continuous time applications. The new structure design and design equations is clarified with the help of a design example of second order continuous time modulator. Then, the proposed architecture is used to implement a more complex third order, 1.5 bit quantizer V4 modulator. The modulator is implemented in a 65nm CMOS technology and can achieves a SNDR of 66 dB for a 5 MHz BW input signal while consuming only 1.5 mW from a 0.9 V single supply. Hence, achieving a Figure of Merit (FoM) of 92 fJ/Conv | ||
| 530 | _aIssued also as CD | ||
| 653 | 4 | _aAnalog to Digital Converter | |
| 653 | 4 | _aRing Amplifier | |
| 653 | 4 | _aSigma-Delta ADC | |
| 700 | 0 |
_aAhmed Nader Mohi Eldin , _eSupervisor |
|
| 700 | 0 |
_aFaisal A. Hussien , _eSupervisor |
|
| 700 | 0 |
_aMohamed M. Aboudina , _eSupervisor |
|
| 856 | _uhttp://172.23.153.220/th.pdf | ||
| 905 |
_aNazla _eRevisor |
||
| 905 |
_aShimaa _eCataloger |
||
| 942 |
_2ddc _cTH |
||
| 999 |
_c70052 _d70052 |
||