| 000 | 01928cam a2200337 a 4500 | ||
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| 003 | EG-GiCUC | ||
| 005 | 20250223032324.0 | ||
| 008 | 190710s2019 ua dh f m 000 0 eng d | ||
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_aEG-GiCUC _beng _cEG-GiCUC |
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| 041 | 0 | _aeng | |
| 049 | _aDeposite | ||
| 097 | _aM.Sc | ||
| 099 | _aCai01.13.08.M.Sc.2019.Am.E | ||
| 100 | 0 | _aAmr Hassan Ali Baddar | |
| 245 | 1 | 0 |
_aExploring the simulation of dynamic partial reconfiguration for network on chip (NOC)-based FPGA / _cAmr Hassan Ali Baddar ; Supervised Hossam A. H. Fahmy , Hassan Mostafa |
| 246 | 1 | 5 | _aاستكشاف محاكاة إعادة التشكيل الجزئي الديناميكي لتطبيق شبكات توصيل المعلومات على نظم المصفوفات القابله للبرمجه |
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_aCairo : _bAmr Hassan Ali Baddar , _c2019 |
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| 300 |
_a68 P. : _bcharts , facsimiles ; _c30cm |
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| 502 | _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications | ||
| 520 | _aIn this thesis, a literature survey of exiting Dynamic Partial Reconfiguration (DPR) techniques forconventional FPGAsis presented. Then, a comparative review ofthese techniques is providedwith respect to reconfiguration time and area. Following that, different network parameters at the NoC-based FPGAs have been analyzed to estimate the impact on DPR performance usinga state-of-art simulator2NoC-DPR3, Finally, a case study is introduced to clarify the DPR performancegap between NoC-based FPGAs and conventional FPGAs | ||
| 530 | _aIssued also as CD | ||
| 653 | 4 | _aDynamic Partial Reconfiguration | |
| 653 | 4 | _aFields Programmable Gate Array | |
| 653 | 4 | _aNetwork-on-Chip | |
| 700 | 0 |
_aHassan Mostafa , _eSupervisor |
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| 700 | 0 |
_aHossam A. H. Fahmy , _eSupervisor |
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| 856 | _uhttp://172.23.153.220/th.pdf | ||
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_aNazla _eRevisor |
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_aShimaa _eCataloger |
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_2ddc _cTH |
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_c72741 _d72741 |
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