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| 003 | EG-GiCUC | ||
| 005 | 20250223032713.0 | ||
| 008 | 210308s2020 ua dh f m 000 0 eng d | ||
| 040 |
_aEG-GiCUC _beng _cEG-GiCUC |
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| 041 | 0 | _aeng | |
| 049 | _aDeposite | ||
| 097 | _aPh.D | ||
| 099 | _aCai01.13.08.Ph.D.2020.Na.A | ||
| 100 | 0 | _aNariman Abdo Khalil Hussein | |
| 245 | 1 | 0 |
_aApplications of fractional order elements and mem-elements in electronic circuits / _cNariman Abdo Khalil Hussein ; Supervised Ahmed Mohamed Soliman , Ahmed Gomaa Radwan , Lobna Ahmed Said |
| 246 | 1 | 5 | _aتطبيقات العناصر الكسرية والعناصر التخزينية الكسرية فى الدوائر الإلكترونية |
| 260 |
_aCairo : _bNariman Abdo Khalil Hussein , _c2020 |
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| 300 |
_a186 P. : _bcharts , facsimiles ; _c30cm |
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| 502 | _aThesis (Ph.D.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications | ||
| 520 | _aThis work aims to apply the fractional-order elements and mem-elements in analog circuit design. A general {u200E}prototype fractional-order {uFB01}lter based on a two-port network concept with four external impedances is {u200E}investigated. Ten possible generalized topologies are introduced where the necessary network conditions and {u200E}the critical frequencies are presented. Besides, a generalized prototype topology of fractional order inverse {u200E}{uFB01}lters (FOIF) is presented based on operational trans-resistance ampli{uFB01}ers and second-generation {u200E}current conveyor.The fractional-order parameters increase design {uFB02}exibility and controllability, which is {u200E}validated experimentally.The fractional-order systems are extended to memristive element modeling. The {u200E}realization of grounded and {uFB02}oating fractional-order mem-elements (FOMEs) using the generalized emulator.{u200E}Two- and three-port mutators are used to realize different FOMEs employing di{uFB00}erent combinations of impedances.The FOMEs are applied to Chau's circuit showing the effect of fractional-order on the chaotic behavior. Circuit {u200E}simulations and experimental results for the presented circuits are introduced to validate the theoretical {u200E}{uFB01}ndings | ||
| 530 | _aIssued also as CD | ||
| 653 | 4 | _aFractional filter and inverse filter | |
| 653 | 4 | _aFractional order elements emulator | |
| 653 | 4 | _aFractional order memelements emulator | |
| 700 | 0 |
_aAhmed Gomaa Radwan , _eSupervisor |
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| 700 | 0 |
_aAhmed Mohamed Soliman , _eSupervisor |
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| 700 | 0 |
_aLobna Ahmed Said , _eSupervisor |
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| 856 | _uhttp://172.23.153.220/th.pdf | ||
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_aNazla _eRevisor |
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| 905 |
_aShimaa _eCataloger |
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_2ddc _cTH |
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_c80179 _d80179 |
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