000 02289cam a2200313 a 4500
003 EG-GiCUC
008 210325s2020 ua d f m 000 0 eng d
040 _aEG-GiCUC
_beng
_cEG-GiCUC
041 0 _aeng
049 _aDeposite
097 _aM.Sc
099 _aCai01.13.08.M.Sc.2020.Ka.L
100 0 _aKareem Ramadan Mahmoud Rashed
245 1 0 _aLow-noise wide-bandwidth phase-domain all-digital fractional-n phase-locked loop /
_cKareem Ramadan Mahmoud Rashed ; Supervised Ahmed Nader Mohieldin , Faisal Abdellatif Hussien
246 1 5 _aحلقة مقفلة الطور كسرية طورية رقمية بالكامل ذات ضوضاء منخفضة ونطاق واسع
260 _aCairo :
_bKareem Ramadan Mahmoud Rashed ,
_c2020
300 _a112 P . :
_bcharts ;
_c30cm
502 _aThesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications
520 _aIn this thesis, an ADPLL that employs a high-resolution TDC and a highlinearity DTC to achieve low in-band phase noise and spurs with wide bandwidth and low power consumption is presented. The TDC/DTC set is implemented in TSMC-40nm CMOS process. A time-amplifier based TDC (TA-TDC) is utilized to achieve a sub-gate delay resolution of 3.2 pS. The TA-TDC achieves an integral nonlinearity (INL) less than 0.5 LSB and power consumption of 108 uW. A constant-slope DTC (CS-DTC) that leverages the concept of charge redistribution is proposed. The CS-DTC achieves 0.3 LSB INL. Consequently, a fractional spur of level better than -48 dBc/Hz is expected at the PLL output. The DTC achieves 1.7 pSrms integrated jitter which dominates the in-band phase noise of the PLL. The CS-DTC consumes only 8 uA from 1.1 V supply. The PLL was able to achieve 1.44 MHz bandwidth at 2.5 GHz output frequency using 50 MHz reference. The PLL achieves better than -106 dBc/Hz in-band phase noise which translates to an integrated RMS-jitter of 682 fS
530 _aIssued also as CD
653 4 _aAll-Digital Phase-Locked Loop (ADPLL)
653 4 _aLow Power
653 4 _aWide Bandwidth
700 0 _aAhmed Nader Mohieldin ,
_eSupervisor
700 0 _aFaisal Abdellatif Hussien ,
_eSupervisor
905 _aAmira
_eCataloger
905 _aNazla
_eRevisor
942 _2ddc
_cTH
999 _c80362
_d80362