Thesis (M.Sc.) - Cairo University - Faculty Of Engineering - Department Of Mathematics and Physics

The advent of the nanotechnology has introduced new challenges and non - conventional problems to High Speed Digital VLSI designMoreover , the relentless progress of manufacturing technology is widening the gap between current CAD tools and VLSI technologiesThis is reflected clearly in the IC design process where the IC flow has become very iterative , especially in the backend phaseThis returns to the complexity of placement and routing phases and the inadequate approximations used for interconnect modelingHence , we introduce a new approach to complete the routing without or with minimal iterationsInstead of employing the traditional flow that uses inaccurate interconnect modeling and then analyze the output to point out errors in the resulting routing , we propose Interconnect Synthesis as a new approachIn this approach , we introduce an enhanced routing algorithm that outperforms traditional routers and present a more accurate interconnect modeling and signal characterization techniques to avoid inaccuracies affecting the routing algorithmConsequently , the output of the routing phase will no longer suffer from the errors in the timing or the signal integrity constraintsFinally , the analysis phase will become merely a verification phase , not a process for re - iterations

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