Asic design of all digital pll{u2019}s for processors-clock generation /
Ezz Eldin Omar Ahmed Hussein Hamed
Asic design of all digital plls for processors-clock generation / تصميم دائرة رقمية بالكامل لضبط طور إشارة الساعة لمشغل دقيق Ezzeldin Omar Ahmed Hussein Hamed ; Supervised Serag E. D. Habib , Hanan A. Kamal - Cairo : Ezz Eldin Omar Ahmed Hussein Hamed , 2012 - 61 P. : facsimiles ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
All Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks mainly to their scalability across technology nodes. This work presents a new standard-cell based ADPLL for processors clock generation. The target technology is TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800 MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These features make the proposed ADPLL design very suitable for SoC applications
ADPLL Bang-Bang Synthesizable PLL
Asic design of all digital plls for processors-clock generation / تصميم دائرة رقمية بالكامل لضبط طور إشارة الساعة لمشغل دقيق Ezzeldin Omar Ahmed Hussein Hamed ; Supervised Serag E. D. Habib , Hanan A. Kamal - Cairo : Ezz Eldin Omar Ahmed Hussein Hamed , 2012 - 61 P. : facsimiles ; 30cm
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
All Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks mainly to their scalability across technology nodes. This work presents a new standard-cell based ADPLL for processors clock generation. The target technology is TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800 MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These features make the proposed ADPLL design very suitable for SoC applications
ADPLL Bang-Bang Synthesizable PLL