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Asic design of all digital pll{u2019}s for processors-clock generation / (Record no. 50066)

MARC details
000 -LEADER
fixed length control field 01824cam a2200337 a 4500
003 - CONTROL NUMBER IDENTIFIER
control field EG-GiCUC
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20250223031202.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 150326s2012 ua h f m 000 0 eng d
040 ## - CATALOGING SOURCE
Original cataloging agency EG-GiCUC
Language of cataloging eng
Transcribing agency EG-GiCUC
041 0# - LANGUAGE CODE
Language code of text/sound track or separate title eng
049 ## - LOCAL HOLDINGS (OCLC)
Holding library Deposite
097 ## - Thesis Degree
Thesis Level M.Sc
099 ## - LOCAL FREE-TEXT CALL NUMBER (OCLC)
Classification number Cai01.13.08.M.Sc.2012.Ez.A
100 0# - MAIN ENTRY--PERSONAL NAME
Personal name Ezz Eldin Omar Ahmed Hussein Hamed
245 10 - TITLE STATEMENT
Title Asic design of all digital pll{u2019}s for processors-clock generation /
Statement of responsibility, etc. Ezzeldin Omar Ahmed Hussein Hamed ; Supervised Serag E. D. Habib , Hanan A. Kamal
246 15 - VARYING FORM OF TITLE
Title proper/short title تصميم دائرة رقمية بالكامل لضبط طور إشارة الساعة لمشغل دقيق
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Cairo :
Name of publisher, distributor, etc. Ezz Eldin Omar Ahmed Hussein Hamed ,
Date of publication, distribution, etc. 2012
300 ## - PHYSICAL DESCRIPTION
Extent 61 P. :
Other physical details facsimiles ;
Dimensions 30cm
502 ## - DISSERTATION NOTE
Dissertation note Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
520 ## - SUMMARY, ETC.
Summary, etc. All Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks mainly to their scalability across technology nodes. This work presents a new standard-cell based ADPLL for processors{u2019} clock generation. The target technology is TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800 MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These features make the proposed ADPLL design very suitable for SoC applications
530 ## - ADDITIONAL PHYSICAL FORM AVAILABLE NOTE
Additional physical form available note Issued also as CD
653 #4 - INDEX TERM--UNCONTROLLED
Uncontrolled term ADPLL
653 #4 - INDEX TERM--UNCONTROLLED
Uncontrolled term Bang-Bang
653 #4 - INDEX TERM--UNCONTROLLED
Uncontrolled term Synthesizable PLL
700 0# - ADDED ENTRY--PERSONAL NAME
Personal name Hanan A. Kamal ,
Relator term
700 0# - ADDED ENTRY--PERSONAL NAME
Personal name Serag E. D. Habib ,
Relator term
856 ## - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://172.23.153.220/th.pdf">http://172.23.153.220/th.pdf</a>
905 ## - LOCAL DATA ELEMENT E, LDE (RLIN)
Cataloger Aml
Reviser Cataloger
905 ## - LOCAL DATA ELEMENT E, LDE (RLIN)
Cataloger Nazla
Reviser Revisor
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Thesis
Holdings
Source of classification or shelving scheme Not for loan Home library Current library Date acquired Full call number Barcode Date last seen Koha item type Copy number
Dewey Decimal Classification   المكتبة المركزبة الجديدة - جامعة القاهرة قاعة الرسائل الجامعية - الدور الاول 11.02.2024 Cai01.13.08.M.Sc.2012.Ez.A 01010110064836000 22.09.2023 Thesis  
Dewey Decimal Classification   المكتبة المركزبة الجديدة - جامعة القاهرة مخـــزن الرســائل الجـــامعية - البدروم 11.02.2024 Cai01.13.08.M.Sc.2012.Ez.A 01020110064836000 22.09.2023 CD - Rom 64836.CD