Low energy computer architecture designs /
Mervat Mohamed Adel Mahmoud
Low energy computer architecture designs / تصميمات منخفضة الطاقة لبنية الحاسب Mervat Mohamed Adel Mahmoud ; Supervised Hossam A. H. Fahmy , Dalia A. Eldib - Cairo : Mervat Mohamed Adel Mahmoud , 2019 - 69 P. : charts , facsimiles ; 30cm
Thesis (Ph.D.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
The continuous increase in chip integration and the associated energy consumption concerns made low power/energy design one of the main challenges facing VLSI systems. A low energy clock-gated pipelined dual base binary/decimal fixed-point multiplier is suggested extending a previously proposed non-pipelined design. A thorough study conducted on both the pipelined and non-pipelined designs versus other architectures in literature proves tremendous reductions in power, energy and area consumption.In addition, a new low energy lossless compression/decompression approach is suggested for main memory data. The proposed design lowers energy consumption due to its simplicity and low latency
Low energy Parallel architectures Pipeline processing
Low energy computer architecture designs / تصميمات منخفضة الطاقة لبنية الحاسب Mervat Mohamed Adel Mahmoud ; Supervised Hossam A. H. Fahmy , Dalia A. Eldib - Cairo : Mervat Mohamed Adel Mahmoud , 2019 - 69 P. : charts , facsimiles ; 30cm
Thesis (Ph.D.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
The continuous increase in chip integration and the associated energy consumption concerns made low power/energy design one of the main challenges facing VLSI systems. A low energy clock-gated pipelined dual base binary/decimal fixed-point multiplier is suggested extending a previously proposed non-pipelined design. A thorough study conducted on both the pipelined and non-pipelined designs versus other architectures in literature proves tremendous reductions in power, energy and area consumption.In addition, a new low energy lossless compression/decompression approach is suggested for main memory data. The proposed design lowers energy consumption due to its simplicity and low latency
Low energy Parallel architectures Pipeline processing