Enhanced performance of Cairo University SPARC processor at 65nm node / Alhassan Mohamed Fattin Mohamed Zaki Khedr ; Supervised Serag E. D. Habib
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TextLanguage: English Publication details: Cairo : Alhassan Mohamed Fattin Mohamed Zaki Khedr , 2011Description: 84P. : charts , plans ; 30cmOther title: - تحسين أداء معالج SPARC المطور بجامعة القاهرة بتكنولوجيا 65 نانومتر [Added title page title]
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قاعة الرسائل الجامعية - الدور الاول | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2011.Al.E (Browse shelf(Opens below)) | Not for loan | 01010110057974000 | ||
CD - Rom
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مخـــزن الرســائل الجـــامعية - البدروم | المكتبة المركزبة الجديدة - جامعة القاهرة | Cai01.13.08.M.Sc.2011.Al.E (Browse shelf(Opens below)) | 57974.CD | Not for loan | 01020110057974000 |
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| Cai01.13.08.M.Sc.2011.Ah.P Particle swarm optimization algorithms for object tracking / | Cai01.13.08.M.Sc.2011.Ah.P Particle swarm optimization algorithms for object tracking / | Cai01.13.08.M.Sc.2011.Al.E Enhanced performance of Cairo University SPARC processor at 65nm node / | Cai01.13.08.M.Sc.2011.Al.E Enhanced performance of Cairo University SPARC processor at 65nm node / | Cai01.13.08.M.Sc.2011.Am.F Fabrication and testing of Cairo University SPARC "CUSPARC" processor / | Cai01.13.08.M.Sc.2011.Am.F Fabrication and testing of Cairo University SPARC "CUSPARC" processor / | Cai01.13.08.M.Sc.2011.Am.V Verification of decimal floating-point operations / |
Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication
Several enhancements to the CUSPARC design are reported in this rhesis . First , to enhance its DSP performance , the CUSPARC design is augmented with an energy efficient 32 - bit integer multiplier. Second, the source code of the GCC compiler is customized to support the added multiplier. Third, the processor design is ported to the TSMC 65nm CMOS technology node
Issued also as CD
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