header
Local cover image
Local cover image
Image from OpenLibrary

Exploring the simulation of dynamic partial reconfiguration for network on chip (NOC)-based FPGA / Amr Hassan Ali Baddar ; Supervised Hossam A. H. Fahmy , Hassan Mostafa

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Amr Hassan Ali Baddar , 2019Description: 68 P. : charts , facsimiles ; 30cmOther title:
  • استكشاف محاكاة إعادة التشكيل الجزئي الديناميكي لتطبيق شبكات توصيل المعلومات على نظم المصفوفات القابله للبرمجه [Added title page title]
Subject(s): Online resources: Available additional physical forms:
  • Issued also as CD
Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications Summary: In this thesis, a literature survey of exiting Dynamic Partial Reconfiguration (DPR) techniques forconventional FPGAsis presented. Then, a comparative review ofthese techniques is providedwith respect to reconfiguration time and area. Following that, different network parameters at the NoC-based FPGAs have been analyzed to estimate the impact on DPR performance usinga state-of-art simulator2NoC-DPR3, Finally, a case study is introduced to clarify the DPR performancegap between NoC-based FPGAs and conventional FPGAs
Tags from this library: No tags from this library for this title. Log in to add tags.
Star ratings
    Average rating: 0.0 (0 votes)
Holdings
Item type Current library Home library Call number Copy number Status Barcode
Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2019.Am.E (Browse shelf(Opens below)) Not for loan 01010110078589000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2019.Am.E (Browse shelf(Opens below)) 78589.CD Not for loan 01020110078589000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

In this thesis, a literature survey of exiting Dynamic Partial Reconfiguration (DPR) techniques forconventional FPGAsis presented. Then, a comparative review ofthese techniques is providedwith respect to reconfiguration time and area. Following that, different network parameters at the NoC-based FPGAs have been analyzed to estimate the impact on DPR performance usinga state-of-art simulator2NoC-DPR3, Finally, a case study is introduced to clarify the DPR performancegap between NoC-based FPGAs and conventional FPGAs

Issued also as CD

There are no comments on this title.

to post a comment.

Click on an image to view it in the image viewer

Local cover image