Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication

In this thesis, I propose a novel fully integrated scalable multi - channel clock and data recovery design that realizes significant area and power savings to bring Tbps (tera - bits - per - second ) communication within reach and make it an integrable function at the periphery of high - speed systems and SoCs . The proposed chip design exploits the synchrony of multiple point - to - point optical or inter - chip links and constructs a novel scalable architecture that saves on chip area by using a single VCO block to drive multiple phase detection loops

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