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Enhanced performance of Cairo University SPARC processor at 65nm node / Alhassan Mohamed Fattin Mohamed Zaki Khedr ; Supervised Serag E. D. Habib

By: Contributor(s): Material type: TextTextLanguage: English Publication details: Cairo : Alhassan Mohamed Fattin Mohamed Zaki Khedr , 2011Description: 84P. : charts , plans ; 30cmOther title:
  • تحسين أداء معالج SPARC المطور بجامعة القاهرة بتكنولوجيا 65 نانومتر [Added title page title]
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  • Issued also as CD
Dissertation note: Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication Summary: Several enhancements to the CUSPARC design are reported in this rhesis . First , to enhance its DSP performance , the CUSPARC design is augmented with an energy efficient 32 - bit integer multiplier. Second, the source code of the GCC compiler is customized to support the added multiplier. Third, the processor design is ported to the TSMC 65nm CMOS technology node
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Item type Current library Home library Call number Copy number Status Barcode
Thesis Thesis قاعة الرسائل الجامعية - الدور الاول المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2011.Al.E (Browse shelf(Opens below)) Not for loan 01010110057974000
CD - Rom CD - Rom مخـــزن الرســائل الجـــامعية - البدروم المكتبة المركزبة الجديدة - جامعة القاهرة Cai01.13.08.M.Sc.2011.Al.E (Browse shelf(Opens below)) 57974.CD Not for loan 01020110057974000

Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communication

Several enhancements to the CUSPARC design are reported in this rhesis . First , to enhance its DSP performance , the CUSPARC design is augmented with an energy efficient 32 - bit integer multiplier. Second, the source code of the GCC compiler is customized to support the added multiplier. Third, the processor design is ported to the TSMC 65nm CMOS technology node

Issued also as CD

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