Thesis (M.Sc.) - Cairo University - Faculty of Engineering - Department of Electronics and Communications

In this thesis, a low-power all-digital phase-locked loop (ADPLL) is presented to be used as a frequency synthesizer in low-power applications. The PLL utilizes sub-sampling operation to maintain low power consumption. A novel technique is proposed to extend the loop{u2019}s lock-in range. This technique allows the loop to tolerate 10x larger frequency disturbances without losing locking. The main analog blocks are designed in a 40nm CMOS technology. A new time to digital converter (TDC) architecture based on a multi-path delay line is introduced. The new architecture allows the TDC to achieve high resolution while keeping a low power consumption. An 8-bit segmented digital to time converter (DTC) is designed. The DTC achieves relatively good linearity while consuming low power. A low-power digitally-controlled oscillator (DCO) is implemented and it achieves better than -114dBc/Hz phase noise at 1MHz offset. The estimated PLL phase noise at 1MHz offset is around -109dBc/Hz

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